Many parallel processors resolve data dependencies by employing register renaming. Various register renaming techniques are known in the art. One fundamental renaming scheme is described by Hennessy and Patterson, in “Computer Architecture—A Quantitative Approach,” Fifth edition, Morgan Kaufmann, September, 2011, chapter 3, which is incorporated herein by reference. An overview of known renaming schemes is given, for example, by Sima in “The Design Space for Register Renaming Techniques,” IEEE Micro, September, 2000, pages 70-83, which is incorporated herein by reference. Other renaming schemes are described by Monreal et al., in “Dynamic Register Renaming Through Virtual-Physical Registers,” Journal of Instruction-Level Parallelism, volume 2, 2000, which is incorporated herein by reference.